1. Technical Field
An embodiment of the present invention described herein relates generally to a semiconductor apparatus, and more particularly, to a data input circuit of a semiconductor apparatus.
2. Related Art
A typical semiconductor apparatus includes a plurality of data pads and a plurality of data input buffers that are electrically connected to the data pads in order to perform a data input operation. The plurality of data input buffers perform a buffering operation on data input through the data pads in response to internal clocks. In order that the buffering operation of the data input buffer is performed in the desired manner, the timings of the internal clocks and the data transferred to the data input buffer should be as closely matched as possible.
The difference between these timings at which the semiconductor apparatus still performs normally is dependent upon the speed of operation. In general, as the operation speed of the semiconductor apparatus increases, the permitted difference in timings between the internal clocks and the data transferred to each data input buffer is gradually reduced. In addition, a timing margin is reduced due to a skew difference in the internal clocks transferred to each data input buffer. Thus, as the operation speed of the semiconductor apparatus increases, it becomes more difficult to secure the stable operation of the data input circuit.
In order to solve the above problems, the components of a conventional semiconductor apparatus are arranged so that each data input buffer is disposed adjacent to one other. Further, the lengths of the input lines of data are configured to be equal to each other so that the distance between the respective data pads and their corresponding data input buffers are uniform.
The data input circuit of the conventional semiconductor apparatus will be described in detail with reference to FIG. 1. FIG. 1 is a diagram showing a configuration disclosed in Korean Patent Publication No. 10-1999-0057223.
FIG. 1 is a configuration diagram of the data input circuit of the conventional semiconductor apparatus. For convenience of explanation, FIG. 1 schematically shows only configurations of buffering the data input through five data pads.
Referring to FIG. 1, the data input circuit of the conventional semiconductor apparatus is provided with five data pads 1-1 to 1-5. Each data pad 1-1 to 1-5 is electrically connected to one of five data input buffers 3-1 to 3-5 through one of the data lines 2-1 to 2-5. Five data input buffers 3-1 to 3-5 buffer input data ‘din1’ to ‘din5’ transferred through the data lines 2-1 to 2-5 and output the buffered data ‘dbuf1’ to ‘dbuf5’. In order to perform the buffering operation, five data input buffers 3-1 to 3-5 receive an internal clock ‘clk_int’.
As shown in FIG. 1, the five data input buffers 3-1 to 3-5 are arranged to be adjacent to each other. Therefore, although the internal clock ‘clk_int’ is implemented as a high frequency clock, the timing difference between the data transferred to each data input buffer 3-1 to 3-5 is minimal. All of the five data lines 2-1 to 2-5 provided amongst the five data pads 1-1 to 1-5 and five data input buffers 3-1 to 3-5 have the same length. As shown, the five data lines 2-1 to 2-5 each have different shapes, includes a twisted type shape, in order to achieve equal lengths. The additional turns of the data lines required to accomplish equal lengths consume additional space in the semiconductor apparatus. Furthermore, coupling noise may occur due to the twisted shape of certain ones of the data lines 2-1 to 2-5.